1. Field of the Invention
The present invention relates generally to semiconductor devices and, more particularly, to an integrated circuit (IC) package or semiconductor package including integrated spark or arc gaps which are uniquely configured to reduce the susceptibility of the package to being damaged from an electrostatic discharge (ESD) event.
2. Description of the Related Art
Many modem applications for semiconductor packages target environments where the package is exposed to intense electromagnetic fields that can lead to electrostatic discharge (ESD) events which are known to damage the normal operation thereof. Currently, a large market for manufactured semiconductor package is appliances, both residential and commercial. These particular applications typically pose unique challenges, especially those that expose the package to strong electromagnetic fields and eddy current induced magnetic fields. Often, these fields are strong enough to create an electrostatic discharge that dissipates through the application printed circuit board (PCB) or even within the interior of a semiconductor package, thus damaging or affecting the operation thereof and/or other devices in the application. Along these lines, imperfections in normal printed circuit board or silicon die manufacturing will periodically produce devices that are imperfect, and susceptible to damage when exposed to static electric and high current fields. ESD problems are also increasing in the electronics industry as a result of the trends toward higher speed and smaller semiconductor device or package sizes.
In general terms, an electrostatic discharge or ESD event is the sudden transition of electric current that flows between two objects at different electrical potential. In terms of semiconductor packages, ESD also refers to momentary, unwanted currents that may cause damage to the semiconductor package and/or the application including the same. ESD is often considered a subset of a more general range of failures associated with electrical over stress (EOS) which is the most frequently occurring failure mode in semiconductor packages of all types. However, EOS is generally associated with over-voltage and over-current stress of rather long time durations, which typically occur during normal circuit operation, screening or test conditions. On the other hand, an ESD event is typically viewed in terms of short, fast and high amplitude pulses that are an inevitable part of the day to day environment. In this regard, ESD is often viewed as a miniature spark of charge that moves between two surfaces that have different potentials. It can occur only when the voltage differential between the two surfaces is sufficiently high to break down the dielectric strength of the medium separating the two surfaces. When a static charge moves within the environment of a semiconductor package, it becomes a current that often damages or destroys gate oxide, metallization, and junctions. The four most common causes of ESD in the context integrated circuit packages or semiconductor packages are a charged body touching the package, a charged package touching a grounded surface, a charged machine touching a package, or an electrostatic field inducing a voltage across a dielectric of the package sufficient to break it down.
In view of the foregoing, various methods have been implemented in the electronic arts to dissipate or null the effects of an ESD event on a semiconductor package. More particularly, in applications where exposure to strong electromagnetic fields is anticipated, extreme and costly measures are often employed to protect the semiconductor package from damage. Exemplary methods for protecting semiconductor packages from ESD damage when exposed to electrostatic charges include incorporating modifications to the PCB design and/or interconnect methods employed to the board level. These “contact points” expose the application PCB and semiconductor package(s) to the external environment and, hence, any electrostatic discharge events that may occur. Though often effective, these techniques typically only address the case where the stray charges enter an application as a result of human contact.
In another example, specialized ESD circuits (smart fuses) are incorporated into the PCB design to protect the more sensitive circuits from ESD voltages that often occur in the Vdd and Vss supply lines to the PCB. These devices are useful, but add cost to the application PCB and do not offer much protection for field induced ESD events. Other solutions take the form of metal shields interfaced to the semiconductor package(s) or multiple ground plane layers in the PCB.
In other situations, exotic ESD circuits are included in the design of the integrated circuit (IC) or semiconductor die of the semiconductor package. The performance of the ESD circuits is typically measured in what is known as the human body model (HBM) and the machine model (MM). The HBM is the most commonly used model for characterizing the susceptibility of an electronic device to damage from electrostatic discharge, and is a simulation of the discharge which might occur when a human touches an electronic device. The MM simulates a machine discharging accumulated static charge through a device to ground, and is often used in a semiconductor package ESD sensitivity test to simulate a discharge from a large metal machine part, trolley, or object that has become charged to a high voltage. However, ESD circuit designs are typically complex and occupy a considerable amount of die area. They also vary widely in their effectiveness and ability to protect a semiconductor die exposed to an ESD event. Further, as the design technology nodes continue to shrink, so does the effectiveness of these circuits. Along these lines, one of the most common methods utilized for ESD protection of sensitive IC's is the “on chip” method wherein ESD protection is built into the die design and is sized for the wafer technology node being utilized therein. However, a limitation with this method is the die size impact, especially for more advanced nodes of 40 nm and below. Additionally, the use of low k and ultra-low k dielectric materials reduces the effectiveness the ESD protection while requiring additional layers and area to implement. Thus, depending upon the desired protection level, these designs can take considerable amount die area. Further, placement of unrelated circuits near an I/O pad may causes unexpected current paths through interactions and may render the protection circuit ineffective.
The present invention addresses the foregoing issues by integrating spark or arc gaps into the design of the semiconductor package. As a result of such integration, the probability of damage to the integrated circuit or semiconductor die is significantly diminished, thus extending its ability to function in applications that previously were not considered in relation thereto. In addition, by enabling this feature at the package level, more costly solutions for ESD protection can be avoided, further extending the market value for the semiconductor package or device. These, as well as other features and advantages of the present invention will be described in more detail below.
Common reference numerals are used throughout the drawings and detailed description to indicate like elements.